1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly to a DRAM (dynamic random access memory).
2. Description of the Related Art
As shown in FIGS. 5A and 5B, in the conventional general DRAM, a pair of cells, which are formed of a selection transistor T and a capacitor C, is symmetrically provided to sandwich a contact portion N of a bit line BL. Each transistor T is formed to have a MOSFET structure. Also, each transistor T has an insulating film 12 formed on a semiconductor substrate 10 and a gate electrode 14. The gate electrode 14 is formed as a part of a word line WL of each cell.
A diffusion layers 16 and 18, serving as source/drain regions of the transistor T, are formed on the substrate. The diffusion layer 16 or a part thereof contacts the bit line BL. The diffusion layer 18 or a part thereof functions as a lower electrode of the capacitor C. The capacitor C comprises the part of the diffusion layer 18, an insulating film 22 formed on the layer 18, and an upper electrode 24. In the figure, reference numeral 26 denotes an insulating film for an element separation.
In the above-mentioned DRAM structure, the respective elements such as the capacitor C, transistor T, contact portion N of the bit line BL are horizontally arranged to be independent of each other, and a fixed area is occupied by the respective elements. Also, since a certain processing margin is needed between the respective elements, the occupied area, which is necessary for each element, is further increased. Therefore, in order to attain a high degree of integration, each element must be greatly miniaturized. Also, it is necessary to limit the processing margin as much as possible. Due to this, the processing technique becomes very difficult, and the yield is considerably limited.